DEC 57-19400-04 (D4-6901-5)

DEC PDP-11 CPU(left half).  "The Control Chip (DC335) implements the microword access and sequencing functions of the J-11 chip set." (http://www.cpu-collection.de/?l0=co&l1=DEC&l2=PDP-11)

Map:  http://siliconpr0n.org/map/dec/57-19400-04/left/top_metal_mit20x/

Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:dec:57-19400-04 

Tundra CA20C03A

Map: http://siliconpr0n.org/map/tundra/ca20c03a/
Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:tundra:ca20c03a


Corporate headquarters are (were? bought by ON Semi) in Pocatello, Idaho as indicated by the flower / bullet hole / splat:

What caught my interest was that this is a sea-of-gates IC of which I don't see too many.  Marked up layout example with some (not all) transistors marked:

One of the wires to the upper right of Q4 doesn't appear to have a contact.  Not sure whats the deal with that.

In short, a sea of gates designer only creates metal masks to save money.  They pick from a library of predetermined chip sizes and padframes.  Transistors form by routing to the strips of poly crossing the active areas.  Logic gates are separated by occasional gaps in the active areas (as seen above) as well as tying areas high/low to prevent current from flowing.   There is a lot of non-linear routing.  I'm not sure if this is from using a detailed cell lib or if it had a lot of custom layout.  As a result, there are large areas of unused active / poly areas.

ST 24C02

Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:st:24c026
Map: http://siliconpr0n.org/map/st/24c02/top_metal__ns50xu/

I want to do a more detailed writeup at some point but here are some quick thoughts.  This 256 byte EEPROM chip was much larger than I was expecting.  Close up of some of the cells:




The charge pump can be seen in the lower right hand corner which is identified by the large capacitors:

 At a quick look what may be the output there appear to be a "high voltage" diode string:



Another interesting thing is that I'd expect a chip this small to be fully custom due to the volume market it targets.  You can see a fair amount of diagonal routing so presumably that's at least somewhat true.  However. one of the markings of a larger chip are standard cells.  Of course, even in a fully custom chip there are some regular patterns for repeated circuits so I'm really only talking about glue logic.  There are a few rows of what look like standard cells (highlighted in red):

However, notice the one highlighted in green has  slightly different width than the ones below it.  Additionally,the left and right bank don't actually have the same width as the right is a little narrower.  So if they did use standard cells and not so much a standard cell layout methodology they must be from several different sized libraries.

Intel 486DX (80486)

Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:intel:80486dx

Map: http://siliconpr0n.org/map/intel/80486dx/mit5x/

The Intel 80486, more commonly known as an i486, added on chip cache and an FPU over the 80386.  The caches are easily visible as the black areas to the left.  I'm not sure which of the random logic areas are the FPU, maybe a comparison with a 386 would make it obvious.  I assumed there was no 80487, but it looks like there is abeit used in a creative upgrade path where you don't need your CPU anymore.

Intel logo:

And designer initials:



Roughly 70 people working on the chip.  It looks like some have 3 initials to clarify duplicates, but it does make me wonder how it was decided how represented the 2 initial versions.  Also unclear of grouping, is not alphabetical by first or last name.

I was also a bit surprised to see the mask ROM at the bottom.  Maybe microcode?  I don't think Intel microcode could be updated until later but would make sense that it was still easier to design with hard coded microcode.

The die shot also looks similar to the 80486DX2 picture on Wikipedia (CC-BY-SA Matt Britt / Matt Gibbs):

While things are in the same general place it looks like there were some layout changes between the two as components are roughly the same size but look to be laid out a little different.  It also could be a difference between epi and inspection scope illumination.

One interesting thing I found from on the Wikipedia page: "Although the 486 became obsolete for personal computer applications by the mid-1990s, Intel had continued production for use in embedded systems. In May 2006 Intel announced that production of the 80486 would stop at the end of September 2007." Things do stick around longer than you intend.

I have a 20x objective scan (this is 5x objective w/ 10x relay lens for 50x total) where you can actually see all the wires, will try to stitch and post.

Intel 1602A: "2048 BIT ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY"

Map: http://siliconpr0n.org/map/intel/1602a_10x/

Okay, so its really a 1702A, but the datasheet says they are the same die and that's what the die is marked.  With a 1973 die copyright this could be one of the oldest pieces of silicon I have.  Not exactly ightning fast by today's standard, but boasts a "fast programming time" of 2048 bits in 2 minutes ie slightly over 17 bits per seconds or about half a second to burn in each byte.

Intel 80960CF (i960)

Map: http://siliconpr0n.org/map/intel/80960cf/mit5x/

Wiki page:  http://www.siliconpr0n.org/archive/doku.php?id=mcmaster:intel:80960cf

The i960 was a competitor to Intel's x86 processor line.  I've seen them in a number of embedded applications like printers so I guess they had some success.  According to Wikipedia they were phased out in favor of StrongARM.

This specimen is from somewhere in the middle of the lineage.  The die is reasonably large at  11.4 X 15.7 mm (179 mm**2).  Compare to something like the 8051 which has a 3.3 X 3.3 mm die (11 mm).  So, I only scanned this at 5x but you can still see some reasonable detail.  I started a scan at 50x, partially as a stitching challenge, but something shifted about halfway through and went out of focus.  I'll probably still try to stitch the good half and post at some point.  Photographing the whole die at 50x was estimated to take 32 hours and was about 24 hours in when I stopped it.  Even prematurely stopped, this is the largest scan I have ever done and still will yield a 3.5 GP after stitching from about 6200 images.

My thanks to the Lab Rat and friends for the donation.

Xilinx XC4413

Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:xilinx:xc4413&#map

This is a mask programmed version of the XC4013/E FPGA.  I didn't realize Xilinx had ever made mask programmable FPGAs.  Maybe popular for reducing cost by removing the external flash or increased reliability for aero/mil/medical. 

The datasheet still talks about M2/M1/M0 for configuring the device...not sure how many people would order mask ROM part and then select parallel flash or w/e.  Presumably this input is really either "don't care" or potentially should be set to one of the special "reserved" values.  If the latter was the case it could potentially mean that this is an identical chip to the normal version with an all 0 mask.  Although I have a pile of XC4ks I don't have the exact replacement (XC4013/E) to compare it to.