Map: http://siliconpr0n.org/map/tundra/ca20c03a/
Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:tundra:ca20c03a
Corporate headquarters are (were? bought by ON Semi) in Pocatello, Idaho as indicated by the flower / bullet hole / splat:
What caught my interest was that this is a sea-of-gates IC of which I don't see too many. Marked up layout example with some (not all) transistors marked:
One of the wires to the upper right of Q4 doesn't appear to have a contact. Not sure whats the deal with that.
In short, a sea of gates designer only creates metal masks to save money. They pick from a library of predetermined chip sizes and padframes. Transistors form by routing to the strips of poly crossing the active areas. Logic gates are separated by occasional gaps in the active areas (as seen above) as well as tying areas high/low to prevent current from flowing. There is a lot of non-linear routing. I'm not sure if this is from using a detailed cell lib or if it had a lot of custom layout. As a result, there are large areas of unused active / poly areas.
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