CMOSfold

Saturday, August 18, 2012

ENC28J60

http://siliconpr0n.org/map/microchip/enc28j60/top_metal_ns50xu/

Not exactly the best stitch but its been lying around for a while and so figured "why not"

Monday, August 13, 2012

Xilinx XC2000 Logic Cell Arrays (LCA) series: XC2064 and XC2018

XC2064 w/ 20x objective: http://siliconpr0n.org/map/xilinx/xc2064/top_metal_mit20x/

XC2064 (upper left) w/ 50x objective: http://siliconpr0n.org/map/xilinx/xc2064/top_metal_ns50xu_semipol_ul/

XC2018 w/ 20x objective: http://siliconpr0n.org/map/xilinx/xc2018/top_metal_mit20x/

If you've looked at the latest Xilinx datasheet you will be overwhelmed by a sea of features / acronyms: DCMs, PLLs, multipliers, block RAM, 10s of I/O standards, GTP transceivers, and many more. Back in my day (alright, to be honest these chips are older than I am) there were just IOBs, CLBs, and interconnect. Heck, I don't think there was even dedicated clock routing. The best you had were longer wires. I don't see any mention of HDL either in the XACT users manual, I think these were schematic driven and sometimes routed by hand. Finally, I guess the term FPGA hadn't been coined yet so its actually known as a "Logic Cell Array (LCA)" in the datasheet.

A handful of people have expressed interest in the XC2000 series as its the first FPGA. The first is a XC2064, a 8x8 CLB grid, while the second is its larger brother the XC2018, a 10x10 CLB grid.

Not surprisingly, the cells are nearly the same. The first is an XC2064 CLB and the second is an XC2018 CLB.

I had been hoping this chip was finally going to answer the question of how the Xilinx internal chip numbers map to package numbering. Presumably die numbers are decided by engineering and marketing decides the product name later. The XC2064 roughly matches up and I guess things just diverge from there.

As a process note, the XC2064 had its bond wires "plucked" by about 1 minute in sonicated 10 mL concentrated HCl : 10 mL H2O, :0.5 mL WFNA. The XC2018 was in the same solution for 10 seconds as the first gave too much damage. The power pad (top) had the most severe damage anywhere on the chip where as the pad below is more typical. I will reduce time and/or concentration even further next time.

As a final plug, looking through the ISE 4 user manual, I couldn't help but notice that ISE doesn't change much except for some sometimes useful feature creep crowding up the display. Not that I really mind that, but with ISE's stability problems I can finally confirm my suspicions that its legacy code that likely hasn't had a well deserved rewrite in at least 10 years. I couldn't get the DOS XACT program to run but I sure hope that doesn't look the same at least. However, the message I got when installation failed seems to still be present in ISE so even if its changed appearance its likely kept the same core.

Saturday, August 11, 2012

Low res die shots

Tuesday, July 24, 2012

DEC 57-19400-04 (D4-6901-5)

DEC PDP-11 CPU(left half). "The Control Chip (DC335) implements the microword access and sequencing functions of the J-11 chip set." (http://www.cpu-collection.de/?l0=co&l1=DEC&l2=PDP-11)

Map: http://siliconpr0n.org/map/dec/57-19400-04/left/top_metal_mit20x/

Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:dec:57-19400-04

Sunday, June 17, 2012

Tundra CA20C03A

Map: http://siliconpr0n.org/map/tundra/ca20c03a/
Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:tundra:ca20c03a

Corporate headquarters are (were? bought by ON Semi) in Pocatello, Idaho as indicated by the flower / bullet hole / splat:

What caught my interest was that this is a sea-of-gates IC of which I don't see too many. Marked up layout example with some (not all) transistors marked:

One of the wires to the upper right of Q4 doesn't appear to have a contact. Not sure whats the deal with that.

In short, a sea of gates designer only creates metal masks to save money. They pick from a library of predetermined chip sizes and padframes. Transistors form by routing to the strips of poly crossing the active areas. Logic gates are separated by occasional gaps in the active areas (as seen above) as well as tying areas high/low to prevent current from flowing. There is a lot of non-linear routing. I'm not sure if this is from using a detailed cell lib or if it had a lot of custom layout. As a result, there are large areas of unused active / poly areas.

Saturday, June 9, 2012

ST 24C02

Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:st:24c026
Map: http://siliconpr0n.org/map/st/24c02/top_metal__ns50xu/

I want to do a more detailed writeup at some point but here are some quick thoughts. This 256 byte EEPROM chip was much larger than I was expecting. Close up of some of the cells:

The charge pump can be seen in the lower right hand corner which is identified by the large capacitors:

At a quick look what may be the output there appear to be a "high voltage" diode string:

Another interesting thing is that I'd expect a chip this small to be fully custom due to the volume market it targets. You can see a fair amount of diagonal routing so presumably that's at least somewhat true. However. one of the markings of a larger chip are standard cells. Of course, even in a fully custom chip there are some regular patterns for repeated circuits so I'm really only talking about glue logic. There are a few rows of what look like standard cells (highlighted in red):

However, notice the one highlighted in green has slightly different width than the ones below it. Additionally,the left and right bank don't actually have the same width as the right is a little narrower. So if they did use standard cells and not so much a standard cell layout methodology they must be from several different sized libraries.

Wednesday, May 23, 2012

Intel 486DX (80486)

Wiki: http://siliconpr0n.org/archive/doku.php?id=mcmaster:intel:80486dx

Map: http://siliconpr0n.org/map/intel/80486dx/mit5x/

The Intel 80486, more commonly known as an i486, added on chip cache and an FPU over the 80386. The caches are easily visible as the black areas to the left. I'm not sure which of the random logic areas are the FPU, maybe a comparison with a 386 would make it obvious. I assumed there was no 80487, but it looks like there is abeit used in a creative upgrade path where you don't need your CPU anymore.

Intel logo:

And designer initials:

Roughly 70 people working on the chip. It looks like some have 3 initials to clarify duplicates, but it does make me wonder how it was decided how represented the 2 initial versions. Also unclear of grouping, is not alphabetical by first or last name.

I was also a bit surprised to see the mask ROM at the bottom. Maybe microcode? I don't think Intel microcode could be updated until later but would make sense that it was still easier to design with hard coded microcode.

The die shot also looks similar to the 80486DX2 picture on Wikipedia (CC-BY-SA Matt Britt / Matt Gibbs):

While things are in the same general place it looks like there were some layout changes between the two as components are roughly the same size but look to be laid out a little different. It also could be a difference between epi and inspection scope illumination.

One interesting thing I found from on the Wikipedia page: "Although the 486 became obsolete for personal computer applications by the mid-1990s, Intel had continued production for use in embedded systems. In May 2006 Intel announced that production of the 80486 would stop at the end of September 2007." Things do stick around longer than you intend.

I have a 20x objective scan (this is 5x objective w/ 10x relay lens for 50x total) where you can actually see all the wires, will try to stitch and post.