Friday, January 11, 2013


Everyone's favorite USB-serial adapter. First chip decapped on my new sulfuric-acid process.

The goal of this analysis was to determine for sure whether the FT232R uses a USB microcontroller, perhaps a core from FTDI's Vinculum line. Many competing units such as the MCP2200 do this, but it adds extra complexity and possibly more failure modes.

Chip before decapping

Top metal
The lack of any obvious ROM areas suggest that the FT232R is indeed an ASIC. Major functional blocks: EEPROM (upper left, smaller memory bank), SRAM buffer (upper left, larger memory bank), oscillator and PLL (analog circuitry at upper right), standard logic cell array (at center, most of the chip).

Wiki page:


Saturday, January 5, 2013

New images

Its been a bumpy road getting the microscope back online after camera failure.  However, things are beginning to shape up.  First step in getting running is to clear out the old samples that I've had kicking around decapped but not imaged for a few months.  One of interest is the TI chip with the labels on the pins:

No scale bars on images as I haven't calibrated with the new camera.  More than likely they are very similar to the older objectives though and you should be able to match up with older pictures if you are really curious (appended to files like mitx20x or mit5x).

Saturday, August 18, 2012

Monday, August 13, 2012

Xilinx XC2000 Logic Cell Arrays (LCA) series: XC2064 and XC2018

XC2064 w/ 20x objective:

XC2064 (upper left) w/ 50x objective:

XC2018 w/ 20x objective:

If you've looked at the latest Xilinx datasheet you will be overwhelmed by a sea of features / acronyms: DCMs, PLLs, multipliers, block RAM, 10s of I/O standards, GTP transceivers, and many more.  Back in my day (alright, to be honest these chips are older than I am) there were just IOBs, CLBs, and interconnect.  Heck, I don't think there was even dedicated clock routing.  The best you had were longer wires.  I don't see any mention of HDL either in the XACT users manual, I think these were schematic driven and sometimes routed by hand.  Finally, I guess the term FPGA hadn't been coined yet so its actually known as a "Logic Cell Array (LCA)" in the datasheet.

A handful of people have expressed interest in the XC2000 series as its the first FPGA.  The first is a XC2064, a 8x8 CLB grid, while the second is its larger brother the XC2018, a 10x10 CLB grid.

Not surprisingly, the cells are nearly the same.  The first is an XC2064 CLB and the second is an XC2018 CLB.

I had been hoping this chip was finally going to answer the question of how the Xilinx internal chip numbers map to package numbering.  Presumably die numbers are decided by engineering and marketing decides the product name later.  The XC2064 roughly matches up and I guess things just diverge from there.

As a process note, the XC2064 had its bond wires "plucked" by about 1 minute in sonicated 10 mL concentrated HCl : 10 mL H2O, :0.5 mL WFNA.  The XC2018 was in the same solution for 10 seconds as the first gave too much damage.  The power pad (top) had the most severe damage anywhere on the chip where as the pad below is more typical.  I will reduce time and/or concentration even further next time.

As a final plug, looking through the ISE 4 user manual, I couldn't help but notice that ISE doesn't change much except for some sometimes useful feature creep crowding up the display.  Not that I really mind that, but with ISE's stability problems I can finally confirm my suspicions that its legacy code that likely hasn't had a well deserved rewrite in at least 10 years.  I couldn't get the DOS XACT program to run but I sure hope that doesn't look the same at least.  However, the message I got when installation failed seems to still be present in ISE so even if its changed appearance its likely kept the same core.